Reliability of metal leads in high speed LSI semiconductors using dummy vias

ABSTRACT

A semiconductor device (and method of manufacturing thereof) having metal leads (114+130) with improved reliability, comprising metal leads (114+130) on a substrate 112, a low-dielectric constant material (116) at least between the metal leads (114+130), and dummy vias (122+134) in contact with the metal leads (114+130). Heat from the metal leads (114+130) is transferable to the dummy vias (122+134), and the dummy vias (122+134) are capable of conducting away the heat. The low-dielectric constant material (116) may have a dielectric constant of less than about 3.5. An advantage of the invention is to improve reliability of metal leads in circuits using low-dielectric constant materials, especially in scaled-down circuits that are compact in the horizontal direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

The following U.S. patent applications am commonly assigned and arehereby incorporated herein by reference:

    __________________________________________________________________________    TI Case                                                                            Ser. No.                                                                            Filing Date                                                                         Inventor                                                                              Title                                                __________________________________________________________________________    TI-18509                                                                           08/137,658                                                                          10/15/93                                                                            Jeng    Planarized Structure for Line-                                                to-Line Capacitance                                                           Reduction                                            TI-18867                                                                           08/201,679                                                                          2/25/94                                                                             Jeng et al                                                                            Selective Filling Narrow Gaps                                                 with Low-dielectric-constant                                                  materials                                            TI-18929                                                                           08/202,057                                                                          2/25/94                                                                             Jeng    Planarized Multilevel                                                         Interconnect Scheme with                                                      Embedded Low-Dielectric-                                                      Constant Insulators                                  TI-19068                                                                           08/234,443                                                                          4/28/94                                                                             Cho     Low Dielectric Constant                                                       Insulation in VLSI                                                            applications                                         TI-19071                                                                           08/234,099                                                                          4/27/94                                                                             Havemann                                                                              Via Formation in Polymeric                                                    Materials                                            TI-18941                                                                           08/247,195                                                                          5/20/94                                                                             Gnade et al                                                                           A Low Dielectric Constant                                                     Material for Electronics                                                      Applications                                         TI-19072                                                                           08/246,432                                                                          5/20/94                                                                             Havemann et al                                                                        Interconnect Structure with an                                                Integrated Low Density                                                        Dielectric                                           TI-19305                                                                           08/250,063                                                                          5/27/94                                                                             Havemann et al                                                                        Multilevel Interconnect                                                       Structure with Air Gaps                                                       Formed Between Metal Leads                           TI-19179                                                                           08/250,747                                                                          5/27/94                                                                             Gnade et al                                                                           Low Dielectric Constant                                                       Layers via Immiscible Sol-gel                                                 Processing                                           TI-19150                                                                           08/250,983                                                                          5/31/94                                                                             Numata  Improving Reliability of                                                      Metal Leads in High Speed                                                     LSI Semiconductors using                                                      Dummy Leads                                          TI-18895                                                                           08/251,822                                                                          5/31/94                                                                             Numata  Improving Reliability of                                                      Metal Leads in High Speed                                                     LSI Semiconductors using                                                      Thermoconductive Dielectric                                                   Layer                                                TI-18896                                                                           08/250,888                                                                          5/31/94                                                                             Numata  Improving Reliability of                                                      Metal Leads in High Speed                                                     LSI Semiconductors using                                                      both Dummy Leads and                                                          Thermoconductive Dielectric Layer                    __________________________________________________________________________

FIELD OF THE INVENTION

This invention relates generally to the fabrication of semiconductordevices, and more specifically to semiconductors with submicron spacing(where the conductor width and the conductor-to-conductor spacing areboth less than one micron) and low-dielectric constant materials betweenintermetallic leads.

BACKGROUND OF THE INVENTION

Semiconductors are widely used in integrated circuits for electronicapplications, including radios and televisions. Such integrated circuitstypically use multiple transistors fabricated in single crystal silicon.Many integrated circuits now contain multiple levels of metallizationfor interconnections.

Semiconductor devices are being scaled down in the horizontal dimensionto reduce wafer cost by obtaining more chips per wafer or by increasingcircuit complexity by obtaining more transistors per chip. Althoughsemiconductor devices are being scaled down in the horizontal dimension,semiconductor devices are not generally being scaled down in thevertical dimension (because the current density would exceed reliabilitylimits). Thus, conductors may have a high aspect ratio (ratio ofconductor height to conductor width of greater than one). Withhorizontal scaling, these tall metal leads are being packed closer andcloser together, causing capacitive coupling between the leads to becomethe primary limitation to circuit speed. If line-to-line capacitance ishigh, a likelihood for electrical inefficiencies and inaccuracies exist.Reducing the capacitance within these multi-level metallization systemswill reduce the RC time constant between the lines.

Typically, the material used to isolate metal lines from each other issilicon dioxide. However, the dielectric constant of dense silicon oxidegrown by thermal oxidation or chemical vapor deposition is on the orderof 3.9. The dielectric constant is based on a scale where 1.0 representsthe dielectric constant of a vacuum. Various materials exhibitdielectric constants from very near 1.0 to values in the hundreds.

SUMMARY OF THE INVENTION

Recently, attempts have been made to use low-dielectric constantmaterials to replace silicon dioxide as a dielectric material. The useof low-dielectric constant materials as insulating layers reduces thecapacitance between the lines (or leads), thus reducing the RC timeconstant. It has been found that using materials with dielectricconstants less than about 3.5 sufficiently reduces the RC time constantin typical submicron circuits. As used herein, the term low-dielectricwill refer to a material with a dielectric constant of less than about3.5.

One problem herein is that the decreased thermal conductivity oflow-dielectric constant materials, especially in circuits with highaspect ratio metal leads, may result in metal lead breakage due to theeffects of Joule's heat. The present invention solves this problem byimproving the thermal conductivity of the structure, resulting inimproved reliability of metal leads in structures using low-dielectricconstant materials.

The present invention encompasses a semiconductor device structure (andmethod for manufacturing thereof) having metal leads with improvedreliability, comprising metal leads on a substrate, a low-dielectricconstant material between the metal leads, and dummy vias in contactwith the metal leads. Heat from the metal leads is transferable to thedummy vias, which are capable of thermally conducting the heat away fromthe metal leads. The low-dielectric constant material has a dielectricconstant of less than about 3.5. An advantage of the invention isimproved reliability of metal leads for circuits using low-dielectricconstant materials.

One preferred embodiment of a method according to the present inventioninvolves forming metal leads on a substrate, depositing a low-dielectricconstant material between the metal leads, and forming dummy vias incontact with the metal leads, so that heat from the metal leads istransferable to the dummy vias and conducted away from the leads, andwhere the low-dielectric constant material has a dielectric constant ofless than about 3.5.

Another embodiment of a method according to the present inventioncomprises depositing a metal interconnect layer on a substrate, etchingthe metal interconnect layer in a predetermined pattern to form metalleads, depositing a low-dielectric constant material between the metalleads, depositing an insulating layer over the low-dielectric constantmaterial and the tops of the metal leads, etching the insulating layerto leave channels in the insulating layer abutting the tops of the metalleads, and depositing a metal layer over the insulating layer to fillthe channels and form dummy vias in contact with the tops of the metalleads.

Another embodiment of the invention is a semiconductor device havingmetal leads with improved reliability, comprising a substrate, metalleads on the substrate, a low-dielectric constant material between themetal leads, and dummy vias in contact with the metal leads, whereinheat from the metal leads is transferable to the dummy vias, and wherethe dummy vias are capable of conducting away the heat from the metalleads.

An advantage of the invention is improved reliability of metal leads forcircuits using low-dielectric constant materials. The invention isparticularly beneficial to semiconductors having a combination of metalleads with high aspect ratios and low-dielectric constant materialswhich are more thermally insulating.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which form an integral part of the specification andare to be read in conjunction therewith, and in which like numerals andsymbols are employed to designate similar components in various viewsunless otherwise indicated:

FIGS. 1A-1C are three-dimensional views of a metal lead of asemiconductor wafer, showing the negative effects of Joule's heat;

FIGS. 2A-2D and 3A-3C are cross-sectional elevational views of a firstembodiment of the present invention, showing dummy vias formed incontact with metal leads on a semiconductor wafer to thereby avoid thenegative effects of Joule's heat as depicted in FIG. 1;

FIG. 4 is a perspective view of a first embodiment of the inventiongenerally illustrated in FIG. 3B;

FIG. 5 is a cross-sectional elevational view of a second embodiment ofthe present invention, with dummy vias in contact with both the top andbottom of metal leads;

FIG. 6 is a perspective view of the second embodiment, generallyillustrated in FIG. 5;

FIG. 7 is a cross-sectional elevational view of a third embodiment ofthe present invention, showing dummy vias formed in contact with metalleads on a semiconductor wafer, where the dummy vias are also in contactwith dummy leads in another metal layer;

FIG. 8 is a cross-sectional elevational view of a fourth embodiment, inwhich the vertical heat conduction path extends throughout the entirewafer;

FIG. 9 is a cross-sectional elevational view of a fifth embodiment,which shows the use of a thermoconductive insulating layer; and

FIGS. 10A-10D and 11A-11C are cross-sectional elevational views of asixth embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The making and use of the presently preferred embodiments are discussedbelow in detail. However, it should be appreciated that the presentinvention provides many applicable inventive concepts which can beembodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not delimit the scope of the invention.

The following is a description of several embodiments of the presentinvention, including manufacturing methods. Corresponding numerals andsymbols in the different figures refer to corresponding parts unlessotherwise indicated. Table 1 below provides an overview of the elementsof the embodiments and the drawings.

                                      TABLE 1                                     __________________________________________________________________________         Preferred      Other Alternate                                           Drawing                                                                            or Specific                                                                          Generic Examples or                                               Element                                                                            Examples                                                                             Term    Descriptions                                              __________________________________________________________________________    110         Semiconductor                                                                 wafer                                                             112  Silicon                                                                              Substrate                                                                             May be other metal interconnect layers or                                     semiconductor elements, (e.g., transistors,                                   diodes);                                                                      Oxides;                                                                       Compound semiconductors (e.g., GaAs,                                          InP, Si/Ge, SiC).                                         114  Titanium                                                                             First metal                                                                           Al, Cu, Mo, W, Ti, Si or alloys thereof;                       trilayer                                                                             interconnect                                                                          Polysilicon, silicides, nitrides, carbides;                    (TiN/AlCu/                                                                           portion of                                                                            AlCu alloy with Ti or TiN underlayers;                         TiN)   metal leads                                                                           Metal interconnect layer.                                 116  OSOG   Low-dielectric                                                                        Air gap (also inert gases, vacuum); silica                     (organic                                                                             constant                                                                              aerogel; other aerogels or xerogels;                           spin-on                                                                              material                                                                              fluorinated silicon oxide.                                     glass)                                                                   118  TEOS   Insulating layer                                                                      SiO.sub.2 ; an insulating layer, typically an oxide            (tetraetho-    and preferably having a thickness less than                    xysilane)      the height of metal leads 114                                  silicon                                                                       dioxide                                                                  119  Channels                                                                             Channels                                                                              Holes in insulating layer 118 where dummy                                     vias 122 will be formed                                   120  Tungsten                                                                             Metal layer                                                                           Titanium trilayer (TiN/AlCu/TiN);                                             Cu, Mo, Al, Ti, Si or alloys thereof;                                         Polysilicon, silicides, nitrides, carbides;                                   AlCu alloy with Ti or TiN underlayers.                    122  Tungsten                                                                             Metal layer                                                                           Titanium trilayer (TiN/AlCu/TiN);                                     portion of                                                                            Cu, Mo, Al, Ti, Si or alloys thereof;                                 dummy vias                                                                            Polysilicon, silicides, nitrides, carbides;                                   AlCu alloy with Ti or TiN underlayers.                    124  Aluminum                                                                             Second metal                                                                          Titanium trilayer (TiN/AlCu/TiN or                             alloy  interconnect                                                                          TiN/AlCu/W);                                                          portion of                                                                            Cu, Mo, W, Ti, Si or alloys thereof;                                  functional                                                                            Polysilicon, silicides, nitrides, carbides;                           metal leads                                                                           AlCu alloy with Ti or TiN underlayers;                                        Metal interconnect layer.                                 126  Aluminum                                                                             Second  Titanium trilayer (TiN/AlCu/TiN);                              alloy  Interconnect                                                                          Cu, Mo, W, Ti, Si or alloys thereof;                                  Portion of                                                                            Polysilicon, silicides, nitrides, carbides;                           Dummy leads                                                                           AlCu alloy with Ti or TiN underlayers;                                        Metal interconnect layer.                                 128  AlN    Thermo- Si.sub.3 N.sub.4 ; both AlN and Si.sub.3 N.sub.4                              (e.g., bilayer or                                                     conductive                                                                            trilayer of Si.sub.3 N.sub.4 /AlN/Si.sub.3 N.sub.4);                  insulating layer                                                                      Insulative material with a thermal                                            conductivity 20% larger than the thermal                                      conductivity of low-dielectric constant                                       material 116 and preferably 20% larger                                        than SiO.sub.2 ; annealed SiO.sub.2                       130  Ti     First barrier                                                                         TiN or other Ti alloy;                                                portion of                                                                            Ti/TiN bilayer;                                                       metal leads                                                                           Cu, Mo, W, Al, Si or alloys thereof.                      132  TEOS   Thin insulating                                                                       Other insulative material                                      (tetraetho-                                                                          layer                                                                  xysilane)                                                                     silicon                                                                       dioxide                                                                  134  Ti     Second barrier                                                                        Bilayer of Ti/TiN;                                                    portion of                                                                            TiN or other Ti alloy;                                                dummy vias or                                                                         Cu, Mo, W, Al, Si or alloys thereof.                                  functional                                                                    metal leads                                                       __________________________________________________________________________

An apparently heretofore-unrecognized problem in semiconductor circuits,especially circuits having high aspect ratio conductors withlow-dielectric constant material between conductors, is that thedecreased thermal conductivity of low-dielectric constant materials mayresult in metal lead breakage due to the effects of Joule's heat.Generally, as the dielectric constant of a material decreases, theconductivity of the material is also decreased. Since all metals have acertain amount of electrical resistance, metal leads with currenttherethrough experience heat production proportional to I² R (Joule'slaw). Such heat through a metal lead is known as Joule's heat. TheJoule's heat will raise the metal lead's temperature if the heat isconducted away therefrom at a slower rate than it is produced.

As a metal lead heats locally in one portion along it, the resistance inthat portion rises slightly (due to properties of the metal), causingthe temperature in that portion to rise even more (although slightly).The higher temperature can increase lead resistance and still furtherincrease the local heating. Thus, locally heated metal leads can bedamaged or fractured. The thinner the metal lead, the weaker it is(which is particularly a concern in submicron circuits). The use oflow-dielectric constant materials as insulative layers further presentsa problem, for such materials generally have poor thermoconductivity.With the use of most low-dielectric constant materials, much more of theJoule's heat generated in metal leads of a circuit remains concentratedin the lead itself.

The effect of Joule's heat on a portion 114 of a metal lead is shown inFIGS. 1A-1C. FIG. 1A shows a perspective view of metal lead of asemiconductor wafer (other portions of the wafer are not shown). Thecross-section of the lead is typically rectangular-shaped, with theheight being greater than the width (a high aspect ratio), because ofscale-down. The metal lead has been scaled down in the lateraldirection, but scale-down in the vertical direction is limited byelectrical conductivity requirements of the circuit. When current flowsthrough metal lead, the metal lead is heated. In reality, a metal leadhas thin and fragile portions, causing uneven lead profiles. Suchunevenness cannot be avoided because photolithography and etchingprocesses of metal leads are not ideal. Electromigration, intensified byJoule's heat, causes the metal lead to first weaken, and then thin. Thinand fragile portions of the metal lead become thinner and thinner ascurrent is cycled through the metal lead (FIG. 1B), and electromigrationis even further intensified in this portion. Eventually such leads canbreak, as shown in FIG. 1C, resulting in device failures.

The present invention improves reliability of metal leads in structuresusing low-dielectric constant materials by using dummy vias in contactwith metal leads to improve the thermal conductivity of the structure.FIG. 2A shows a cross-sectional view of a semiconductor wafer 110 havingmetal leads 114+130 formed on a substrate 112. The substrate may, forexample, contain transistors, diodes, and other semiconductor elements(not shown) as are well known in the art. The substrate 112 may alsocontain other metal interconnect layers, and typically contains a topinsulating oxide layer (to prevent leads from shorting to each other insubsequent metal layers). A first barrier layer is deposited over thesubstrate 112. The first barrier layer is preferably comprised oftitanium. A first metal interconnect layer is deposited over the firstbarrier layer. The first metal interconnect layer is preferablycomprised of a TiN/AlCu/TiN trilayer, but may also comprise, forexample, other aluminum alloy multilayers or monolayers. The first metalinterconnect layer and first barrier layer are etched with apredetermined pattern to form etch lines, or metal leads 114+130 (FIG.2A). Each metal lead 114+130 includes a first metal interconnect portion114 and a first barrier portion 130. Some of the metal leads 114+130 maybe in close proximity to each other, for example, 1 μm or less apart.The aspect ratio (height/width) of the metal leads is generally at least1.5, but typically at least 2.0, and more typically at least 3.0.

Low-dielectric constant material 116 is deposited over the metal leads114+130 and substrate 112 (FIG. 2B). The low-dielectric constantmaterial 116 is preferably comprised of an OSOG (organic spin-on glass),but may also be comprised of an aerogel, xerogel, or otherlow-dielectric constant materials which provide a dielectric constant ofless than about 3.5, but preferably less than 3.0, and more preferablyless than 2.5. The OSOG provides a dielectric constant of about 3.0, andis typically spun on by a spin-coater and then cured for half an hour to2 hours at a temperature of 400° C.-450° C. The low-dielectric constantmaterial 116 is then removed (e.g., with a timed etch) from at least thetops of metal leads 114+130 (FIG. 2C). An insulating layer 118(preferably TEOS silicon dioxide) is applied over the exposed tops ofmetal leads 114+130 and low-dielectric constant material 116. Next, theinsulating layer 118 may be planarized, if needed. The insulating layer118 is patterned (for example, a resist, not shown, may be deposited,exposed, and removed) and etched to leave channels 119 where dummy vias122+134 will later be formed (FIG. 2D). Channels for functional vias(not shown) are preferably formed at the same time the channels 119 fordummy vias 122+134 are formed. The channels 119 expose at least the topsof metal leads 114+130 through insulating layer 118.

Second barrier layer 134 may be deposited over the tops of metal leads114+130 and insulating layer 118 (FIG. 3A). Second barrier layer 134 ispreferably titanium but may also be a bilayer of Ti/TiN or other metalalloys. Metal layer 120 is deposited over second barrier layer 134. Themetal layer 120 is preferably tungsten and may be deposited with a CVDprocess, but other metal alloys may be used. The metal layer 120 maythen be removed from the second barrier layer 134, leaving in thechannels 119 portions 122 thereof. Thus, dummy vias 122+134 reside inthe channels 119 in contact with metal leads 114+130 (FIG. 3B). Eachdummy via 122+134 includes a metal layer portion 122 and a secondbarrier portion 134. Since dummy vias 122+134 are comprised of metal,they are excellent thermal conductors. The metal-to-metal contactbetween the dummy vias 122+134 and the metal leads 114+130 provides anexcellent path for thermoconduction. The dummy vias 122+134 conduct awayenough of the Joule's heat from, and prevent damage to, the metal leads114+130 when the device is in operation. Subsequent processing steps maythen be performed, e.g., further deposition and etching ofsemiconductor, insulative and metallic layers. A possible subsequentprocessing step is shown in FIG. 3C, where functional metal leads124+134 are formed in a second metal interconnect layer. The functionalmetal leads 124+134 are comprised of a second barrier portion 134 and asecond metal interconnect portion 124.

A perspective view of the first embodiment is shown in FIG. 4.Preferably, a metal lead 114+130 will have several dummy vias 122+134formed along its length. The more dummy vias 122+134 there are along themetal lead, the more Joule's heat is conducted away from the metal lead114+130. For example, in a submicron circuit, dummy vias 122+134 formedevery 4 μm along the length of a metal lead 114+130 effectively conductsheat away from the metal lead 114+130.

A second embodiment of the present invention is shown in across-sectional elevational view in FIG. 5. In this embodiment, dummyvias 122+134 are formed in contact with both the tops and bottoms ofmetal leads 114. An advantage of the second embodiment is the ability toconduct away more Joule's heat due to the increase of thermoconductivemetal (provided by the dummy vias 122+134) in contact with metal leads114. A perspective view of the second embodiment is shown in FIG. 6.Dummy vias 122+134 may also be formed only on the bottom of the metalleads 114, although preferably not on the first metal layer, to avoiddamage to transistors and other devices on the underlying circuit.

A third embodiment is shown in FIG. 7. After the step shown in FIG. 3B,a second metal interconnect layer is deposited. Dummy leads 126+134 areformed in the second metal interconnect layer, in contact with the dummyvias 122+134. The dummy leads 126+134 are comprised of a second barrierportion 134 and a second metal interconnect portion 126. This structureprovides more metal (from the dummy vias 122+134 and the dummy leads126+134) to conduct away more heat from the metal lead 114+130. Joule'sheat migrates from metal leads 114+130 to dummy vias 122+134 and throughdummy vias 122+134 to dummy leads 126+134. Joule's heat is conductedaway from the metal leads 114+130 by both the dummy vias 122+134 anddummy leads 126+134. (See also U.S. patent application Ser. No.08/250,983, filed on May 31, 1994 by Numata and assigned to TexasInstruments, where dummy leads are formed proximate metal leads).Functional metal leads 124+134 may be formed at the same time dummyleads 126+134 are formed. The functional metal leads 124+134 arecomprised of a second barrier portion 134 and a second metalinterconnect portion 124.

A fourth embodiment is shown in FIG. 8. Multiple layers of dummy vias122+134 and dummy leads 126 are formed in contact with both the tops andbottoms of metal lead 114+130, creating a vertical dummy metal path forJoule's heat conduction. (For clarity, first barrier portions 130 ofmetal leads and second barrier portions 134 of dummy vias are not shownin FIG. 8. Preferably, the sides and bottom of dummy vias contain secondbarrier portion 134). This vertical dummy metal path may extendthroughout the entire semiconductor wafer, and may terminate at thesurface of the wafer to a contact pad which may be connected to othermeans of heat conduction. This embodiment is especially useful as it canbe relatively easily added after thermal problems are uncovered during,e.g., pre-production testing.

A fifth embodiment of the present invention is shown in FIG. 9. Afterthe step shown in FIG. 2C of the first embodiment, thermoconductiveinsulating layer 128, comprised of A1N, for example, is deposited overthe tops of metal leads 114+130 and low dielectric constant material116. The thermoconductive insulating layer 128 is patterned and etchedto leave channels. A second barrier layer is deposited over the tops ofmetal leads 114+130 and thermoconductive insulating layer 128. A metallayer is deposited over second barrier layer (as was shown in FIG. 3A).The second barrier layer and metal layer fill the channels to form dummyvias 122+134 in thermoconductive insulating layer 128, in contact withmetal leads 114+130, shown in FIG. 9. (Refer to U.S. patent applicationSer. No. 08/251,822 filed on May 31, 1994 by Numata for ImprovingReliability of Metal Leads in High Speed LSI Semiconductors UsingThermoconductive Dielectric Layer). Joule's heat from metal leads114+130 is transferred to dummy vias 122+134 and then tothermoconductive insulating layer 128, improving the thermoconductivityof the structure, and thus improving the reliability of the metal leads.Subsequent processing steps as described in other embodiments may thenbe performed.

A sixth embodiment is shown in FIGS. 10A-10D and 11A-11C. In thisembodiment, first barrier layer 130a, e.g., comprised of titanium, isdeposited over the substrate 112 (FIG. 10A). A first metal interconnectlayer 114a is deposited over the first barrier layer 130a. Preferably,the first metal interconnect layer 114a is comprised of a trilayer ofTiN/AlCu/TiN. The trilayer is formed by first depositing titaniumnitride over the first barrier layer using a CVD (chemical vapordeposition) process. Second, AlCu is deposited on the titanium nitrideusing a sputter process; and third, titanium nitride is deposited overthe AlCu with a CVD process.

Next, metal leads 114+130 are formed by selective removal of portions ofthe first metal interconnect layer 114a and the first barrier layer 130a(as shown in phantom), leaving portions of the substrate 112 exposed(FIG. 10A). Each metal lead 114+130 includes a first metal interconnectportion 114 and a first barrier portion 130. A thin insulating layer132, for example, TEOS silicon dioxide, is deposited over metal leads114+130 and exposed portions of the substrate 112 (FIG. 10B).Low-dielectric constant material 116, preferably comprised of OSOG, isdeposited over the thin insulating layer 132 (FIG. 10C) and may beplanarized. Insulating layer 118, preferably TEOS silicon dioxide, isdeposited over low-dielectric constant material 116. Insulating layer118, low-dielectric constant material 116 and thin insulating layer 132are patterned and etched to form channels 119 where dummy vias 122+134will be formed (FIG. 10D). Second barrier layer 134 (preferably abilayer of Ti/TiN, where the Ti is deposited first) is deposited overinsulating layer 118, the tops of metal leads 114+130 and the exposedportions of low-dielectric constant material 116 (FIG. 11A). Metal layer120 is deposited over second barrier layer 134 (FIG. 11B). Metal layer120 fills channels 119 to form dummy vias 122+134. A top portion ofmetal layer 120 is removed, exposing portions of second barrier layer134 residing on top of insulating layer 118, and forming dummy vias122+134 (FIG. 11C). Each dummy via 122+134 includes a metal layerportion 122 and a second barrier portion 134. Portions of second barrierlayer 134 residing on top of insulating layer 118 are left intact untilthe next metal interconnect layer is deposited, so that the secondbarrier layer 134 acts as a thin metal barrier for both the dummy vias122+134 as well as subsequently-formed functional metal leads 124+134(for example, as shown in FIG. 7).

An advantage of dummy vias 122+134 is their ability to create a verticalpath of heat conduction in a semiconductor circuit. This is beneficialto scaled-down circuits where real estate in the horizontal direction isscarce.

An advantage of the present invention over using only dummy leads (as inU.S. patent application Ser. No. 08/250,983 by Numata) is that in somecircuits, them may not be room to form dummy leads proximate to metalleads. Also, the dummy leads, although proximate the metal leads, have adielectric material residing between the dummy leads and the metalleads: thus, dummy vias, which have a metal-to-metal contact to themetal leads, are superior in conducting away the Joule's heat from themetal leads.

An advantage of the present invention over using only a thermoconductiveinsulating layer to conduct away some of the Joule's heat (as in U.S.patent application Ser. No. 08/251,822 by Numata) is that no additionalsteps are required to produce the dummy vias 122+134. Typically,functional vias are made between metal layers of an integrated circuit,and the dummy vias can be formed when the functional vias are formed.

The present invention can also be used on semiconductors using otherlow-dielectric constant materials, such as air gaps, acrogels, xerogels,or fluorinated silicon oxide, for example. To reduce capacitive couplingbetween adjacent leads, low-dielectric constant materials are beinginvestigated, such as pure polymers (e.g., parylene, teflon, polyimide)or organic spin-on glass (OSOG, e.g., silsequioxane or siloxane glass).Refer to U.S. Pat. No. 4,987,101 issued to Kaanta et al on Jan. 22, 1991which describes a method for fabricating gas (air) dielectrics; and U.S.Pat. No. 5,103,288 issued to Sakamoto on Apr. 7. 1992 which describes amultilayered wiring structure which decreases capacitance by using aporous dielectric.

The novel structure and method involving the use of dummy vias 122+134to conduct away Joule's heat from metal leads is particularly beneficialto very compact circuits having no room for dummy leads in the samemetal interconnect, or in adjacent metal interconnect layers. Thepresent invention is also beneficial to semiconductors having submicronspacing and using low-dielectric constant materials. The dummy vias122+134 conduct away a portion of the Joule's heat generated in themetal leads, enhancing reliability of metal leads. The invention isparticularly beneficial to semiconductors having a combination of metalleads with high aspect ratios (e.g., 2 or greater) and low-dielectricconstant materials (especially having a low-dielectric constant of lessthan 2) which are more thermally insulating.

While the invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments. For example, although the effectsof materials having dielectric constants of about 2.5 and concomitantlow thermal conductivities are ameliorated by the present invention, thedummy vias 122+134 hereof are obviously useful to counteract the effectsof any inter-lead dielectric material, the use of which may result inheat damage to the leads due to its low thermoconductivity.

What is claimed is:
 1. A semiconductor device having metal leads withimproved reliability, comprising:a substrate; at least two metal leadson said substrate; a first insulating layer comprising a low-dielectricconstant material between said metal leads, said low-dielectric constantmaterial having a dielectric constant of less than about 3.5; a secondinsulating layer in contact with at least said first insulating layer;first dummy vias formed within said second inflating layer in contactwith said metal leads, wherein heat from said metal leads istransferable to said first dummy vias, and wherein said first dummy viasare capable of conducting said heat away from said metal leads; firstdummy leads in contact with said first dummy vias, wherein heat fromsaid metal leads is transferable to said first dummy leads, and whereinsaid first dummy leads are capable of conducting said heat away fromsaid metal leads; and second dummy vias in contact with said first dummyleads, wherein heat from said metal leads is transferable to said seconddummy leads, and wherein said second dummy vias are capable ofconducting said heat away from said metal leads; wherein said secondinsulating layer is comprised of a thermoconductive material comprisingA1N, Si₃ N₄, or both.